Phase-locked loop (pll)

ABSTRACT

A phase-locked loop (PLL) is provided. The PLL comprises a clock adjuster configured to receive an initial clock signal having an initial frequency and a mode control signal. The clock adjuster is configured to modify the initial clock signal into a modified clock signal based on the mode control signal. The PLL is configured such that a loop bandwidth is equal to a specified bandwidth. When the modified clock signal is changed, a loop gain of a loop filter is adjusted such that the loop bandwidth is substantially equal to the specified bandwidth. When the modified clock signal is changed, an oscillator tuning word (OTW) signal is modified into a normalized OTW signal such that the loop bandwidth is substantially equal to the specified bandwidth.

BACKGROUND

A phase-locked loop (PLL) is a control system that is configured tooutput a signal having a phase that is related to an input signal.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is an illustration of a schematic block diagram, in accordancewith some embodiments.

FIG. 2 is an illustration of a schematic block diagram, in accordancewith some embodiments.

FIG. 3 is an illustration of a schematic block diagram, in accordancewith some embodiments.

FIG. 4 illustrates a method of operating a PLL, in accordance with someembodiments.

FIG. 5 illustrates a method of operating a PLL, in accordance with someembodiments.

FIG. 6 illustrates a method of operating a PLL, in accordance with someembodiments.

FIG. 7 illustrates a method of operating a PLL, in accordance with someembodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components and arrangements are describedbelow to simplify the present disclosure. These are, of course, merelyexamples and are not intended to be limiting. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

In some embodiments, a phase-locked loop (PLL) is provided. In someembodiments, the PLL is an all-digital phase-locked loop (ADPLL). Insome embodiments, the PLL is configured to generate an output clocksignal at an output frequency substantially equal to a target frequency.In some embodiments, the target frequency is constant. In someembodiments, the target frequency changes from a first target frequencyto a second target frequency, and the PLL is configured to change theoutput clock signal in accordance with the change to the targetfrequency. In some embodiments, the PLL is configured to change theoutput clock signal such that the output frequency is substantiallyequal to the second target frequency.

In some embodiments, an initial clock signal is received by a portion ofthe PLL. In some embodiments, the initial clock signal is generated by asignal generator. In some embodiments, a voltage of the initial clocksignal forms a square wave. In some embodiments, the voltage of theinitial clock signal changes between a first voltage level and a secondvoltage level. In some embodiments, a duty cycle of the initial clocksignal is substantially equal to 50%. In some embodiments, the dutycycle of the initial clock signal is below 50%. In some embodiments, theduty cycle of the initial clock signal is above 50%. In someembodiments, the first voltage is substantially equal to 0 V. In someembodiments, the first voltage is above 0 V. In some embodiments, thefirst voltage is below 0 V. In some embodiments, the second voltage isabove 3.3 V. In some embodiments, the second voltage is below 3.3 V. Insome embodiments, the second voltage is substantially equal to 5 V. Insome embodiments, the second voltage is substantially equal to 3.3 V. Insome embodiments, the signal generator is configured to generate theinitial clock signal having characteristics suitable for performance ofthe PLL.

In some embodiments, the signal generator is configured to generate theinitial clock signal having characteristics suitable for performance ofa device other than the PLL. In some embodiments, the initial clocksignal has an initial frequency that is constant. In some embodiments,the initial frequency is below 100 MHz. In some embodiments, the initialfrequency is substantially equal to 100 MHz. In some embodiments, theinitial frequency is substantially equal to 880 MHz. In someembodiments, the initial frequency is between 100 MHz and 1 GHz. In someembodiments, the initial frequency is above 1 GHz. In some embodiments,the initial clock signal is used by the PLL to coordinate one or moreoperations to generate the output clock signal.

In some embodiments, the initial clock signal is used by the PLL togenerate a first clock signal having a first frequency. In someembodiments, the initial clock signal is modified into the first clocksignal. In some embodiments, a duty cycle of the first clock signal issubstantially equal to 50%. In some embodiments, the duty cycle of thefirst clock signal is below 50%. In some embodiments, the duty cycle ofthe first clock signal is above 50%. In some embodiments, the firstfrequency is below the initial frequency. In some embodiments, the firstfrequency is substantially equal to the initial frequency. In someembodiments, the first frequency is above the initial frequency. In someembodiments, the first frequency corresponds to the initial frequencydivided by a specified divisor. In some embodiments, the first frequencyis substantially equal to the initial frequency divided by the specifieddivisor. In some embodiments, increasing the specified divisor resultsin the initial clock signal being modified into a second clock signalhaving a second frequency. In some embodiments, the first frequency isgreater than the second frequency.

In some embodiments, a frequency command word (FCW) signal representinga FCW is received by a portion of the PLL. In some embodiments, the FCWcorresponds to the target frequency. In some embodiments, a change ofthe FCW corresponds to a change to the target frequency. In someembodiments, the FCW is used by the PLL to calculate a reference phaserelated to the target frequency. In some embodiments, the initial clocksignal is used by the PLL to coordinate operations in order to calculatethe reference phase corresponding to the target frequency. In someembodiments, the initial clock signal is used by the PLL to coordinateoperations in order to digitally represent the reference phasecorresponding to the target frequency.

In some embodiments, the PLL is configured to become phase-locked. Insome embodiments, the PLL is phase-locked when there is a constantrelationship between an output phase and the reference phase. In someembodiments, the PLL is phase-locked when the output phase correspondsto the reference phase combined with a phase shift. In some embodiments,the PLL is phase-locked when the output phase is substantially equal tothe reference phase combined with the phase shift. In some embodiments,the phase shift is substantially equal to 0 degrees. In someembodiments, the phase shift is substantially equal to 180 degrees. Insome embodiments, the phase shift is below 180 degrees. In someembodiments, the phase shift is above 180 degrees. In some embodiments,when the PLL is phase-locked, the output frequency is substantiallyequal to the target frequency.

In some embodiments, the PLL is configured to operate such that a loopbandwidth of the PLL is substantially equal to a specified bandwidth. Insome embodiments, the loop bandwidth is a closed-loop bandwidth of thePLL. In some embodiments, the PLL is configured to adjust the loopbandwidth when the loop bandwidth is not substantially equal to thespecified bandwidth. In some embodiments, the loop bandwidth is afunction of the first frequency when the first clock signal isgenerated. In some embodiments, the loop bandwidth is equal to a firstloop bandwidth when the first clock signal is generated. In someembodiments, the loop bandwidth is a function of the second frequencywhen the second clock signal is generated. In some embodiments, the loopbandwidth is equal to a second loop bandwidth when the second clocksignal is generated. In some embodiments, the first loop bandwidth isgreater than the second loop bandwidth, if the first frequency isgreater than the second frequency. In some embodiments, if the secondfrequency is substantially equal to half of the first frequency, thefirst loop bandwidth is two times greater than the second loopbandwidth.

In some embodiments, the loop bandwidth is a function of a parameter ofa loop filter comprised in the PLL. In some embodiments, the parameterof the loop filter is programmable. In some embodiments, the loopbandwidth is a function of a loop gain of the loop filter. In someembodiments, the loop gain is programmable. In some embodiments, theloop bandwidth increases when the loop gain increases. In someembodiments, the loop bandwidth decreases when the loop gain decreases.In some embodiments, when the loop gain is halved, the loop bandwidth ishalved. In some embodiments, when the loop gain is doubled, the loopbandwidth is doubled. In some embodiments, a change of the specifieddivisor from a first specified divisor to a second specified divisorcauses a change of the loop bandwidth from the specified bandwidth to athird loop bandwidth. In some embodiments, in response to the change ofthe loop bandwidth, an adjustment of the loop gain occurs from a firstloop gain to a second loop gain. In some embodiments, the loop bandwidthis substantially equal to the specified bandwidth when the specifieddivisor is the second specified divisor and the loop gain is the secondloop gain. In some embodiments, in response to the change of thespecified divisor the adjustment of the loop gain occurs in order tomitigate the change of the loop bandwidth such that the loop bandwidthis substantially equal to the specified bandwidth when the loop gain isthe second loop gain.

FIG. 1 illustrates a schematic block diagram of a portion of a PLL,according to some embodiments. In some embodiments, the PLL comprises aphase integrator 102, a phase error circuit 104, a mode controller 106,a bandwidth controller 108, a loop filter 110, a normalizer 112, adigitally controlled oscillator (DCO) 114, a clock adjuster 116, a firstportion of a time-to-digital convertor (TDC) 118 and a second portion ofthe TDC 120. In some embodiments, the phase integrator 102 is connectedto the phase error circuit 104, which is connected to the first portionof the TDC 118 and to the second portion of the TDC 120. In someembodiments, an output of the phase error circuit 104 is connected tothe mode controller 106 and to the loop filter 110. In some embodiments,an output of the mode controller 106 is connected to the clock adjuster116 and to the bandwidth controller 108. In some embodiments, the loopfilter 110 is connected to the bandwidth controller 108, to the clockadjuster 116 and to the normalizer 112. In some embodiments, thenormalizer 112 is connected to the bandwidth controller 108, to theclock adjuster 116 and to the DCO 114. In some embodiments, the DCO 114is connected to the first portion of the TDC 118 and to the secondportion of the TDC 120. In some embodiments, the first portion of theTDC 118 is connected to the clock adjuster 116.

In some embodiments, the phase integrator 102 receives a FCW signal S1.In some embodiments, the phase integrator 102 is configured to use theFCW signal S1 to determine a reference phase. In some embodiments, theDCO 114 is configured to output an output clock signal S10 such thatthere is a constant phase difference between an output phase of theoutput clock signal S10 and the reference phase. In some embodiments, ifthere is a constant phase difference between the output phase and thereference phase, the output clock signal S10 has an output frequencythat is substantially equal to a target frequency of the PLL. In someembodiments, the phase difference is substantially equal to 0 degrees.In some embodiments, the phase difference is substantially equal to aphase between 0 degrees and 360 degrees. In some embodiments, the phaseintegrator 102 outputs a reference phase signal S2 based on thereference phase.

In some embodiments, the first portion of the TDC 118 is configured toreceive an initial clock signal S11 and the output clock signal S10. Insome embodiments, the initial clock signal S11 is used by the firstportion of the TDC 118 to coordinate one or more operations to generatea first output phase signal S12 representing an output phase fraction.In some embodiments, the output phase fraction is a calculation of afractional part of the output phase. In some embodiments, the secondportion of the TDC 120 is configured to receive the output clock signalS10. In some embodiments, the second portion of the TDC 120 isconfigured to generate a second output phase signal S13 representing anoutput phase integer. In some embodiments, the initial clock signal S11is used by the second portion of the TDC 120 to coordinate one or moreoperations to generate the second output phase signal S13. In someembodiments, the output phase integer is a calculation of an integerpart of the output phase.

In some embodiments, the phase error circuit 104 is configured toreceive the reference phase signal S2, the first output phase signal S12and the second output phase signal S13. In some embodiments, the phaseerror circuit 104 is configured to output a phase error signal S3 thatrepresents a phase error. In some embodiments, the phase errorcorresponds to a difference between the output phase and the referencephase. In some embodiments, the phase error is substantially equal tothe difference between the output phase and the reference phase. In someembodiments, the phase error circuit 104 is configured to subtract theoutput phase integer and the output phase fraction from the referencephase to determine the phase error. For example, when the output phaseinteger is 17 degrees, the output phase fraction is 0.7 degrees and thereference phase is 20 degrees, the phase error is equal to 20 degreessubtracted by a sum of 17 degrees and 0.7 degrees, which is 2.3 degrees.

In some embodiments, the mode controller 106 is configured to receivethe phase error signal S3. In some embodiments, the mode controller 106is configured to determine if the PLL is phase-locked. In someembodiments, the mode controller 106 is configured to generate a modecontrol signal S4 having a mode value. In some embodiments, the modevalue indicates a mode of operation of the clock adjuster 116.

FIG. 2 illustrates a schematic block diagram of the mode controller 106,according to some embodiments. In some embodiments, the mode controller106 comprises a lock-detection circuit 202 and a finite state machine212. In some embodiments, the lock detection circuit 202 comprises aflip-flop 206, a subtractor 208 and a comparator 210. In someembodiments, the lock-detection circuit 202 is configured to detectwhether the PLL is phase-locked. In some embodiments, the phase errorsignal S3 is received by the flip-flop 206 and by the subtractor 208. Insome embodiments, the flip-flop 206 outputs a stored phase error signalS28 received by the subtractor 208. In some embodiments, the storedphase error signal S28 represents a stored phase error related to thephase error of a preceding clock cycle. In some embodiments, thesubtractor 208 outputs a phase error change signal S15 having a phaseerror change value that corresponds to a difference between the phaseerror and the stored phase error. In some embodiments, the phase errorchange value is substantially equal to the difference between the phaseerror and the stored phase error. In some embodiments, the phase errorchange value decreases when the phase error decreases.

In some embodiments, the phase error change signal S15 is received bythe comparator 210. In some embodiments, the comparator 210 isconfigured to receive a phase error threshold signal S16 having aspecified threshold value. In some embodiments, the comparator 210 isconfigured to output a lock signal S17 having a lock value. In someembodiments, the comparator 210 is configured to output the lock signalS17 having a first value when the phase error change value is above thespecified threshold value. In some embodiments, the comparator 210 isconfigured to output the lock signal S17 having a second value when thephase error change value is below the specified threshold value. In someembodiments, the lock signal S17 having the first value indicates thatthe PLL is not phase-locked. In some embodiments, the lock signal S17having the second value indicates that the PLL is phase-locked. In someembodiments, the finite state machine 212 is configured to receive thelock signal S17. In some embodiments, the finite state machine 212 isconfigured to generate the mode control signal S4 based on the locksignal S17. In some embodiments, the finite state machine 212 isconfigured to change the mode value when the PLL becomes phase-locked.

In FIG. 1, in some embodiments, the clock adjuster 116 receives theinitial clock signal S11. In some embodiments, the clock adjuster 116receives the mode control signal S4. In some embodiments, the clockadjuster 116 is configured to modify the initial clock signal S11 to amodified clock signal S14 based on the mode control signal S4. In someembodiments, when the mode value is a first mode value, the modifiedclock signal S14 is a first clock signal with a first frequency. In someembodiments, when the mode value is a second mode value, the modifiedclock signal S14 is a second clock signal with a second frequency.

In some embodiments, a modified frequency of the modified clock signalS14 corresponds to an initial frequency of the initial clock signal S11divided by a specified divisor. In some embodiments, the modifiedfrequency of the modified clock signal S14 is substantially equal to theinitial frequency of the initial clock signal S11 divided by thespecified divisor. In some embodiments, the specified divisorcorresponds to 2 to the power of the mode value. In some embodiments,the specified divisor is equal to 2 to the power of the mode value. Inthis way, if the mode value is equal to 0, the modified frequencycorresponds to the initial frequency, and if the mode value is equal to1, the modified frequency corresponds to the initial frequency dividedby 2. In some embodiments, if the mode value is equal to 0, the modifiedfrequency is substantially equal to the initial frequency, and if themode value is equal to 1, the modified frequency is substantially equalto the initial frequency divided by 2. In some embodiments, the loopfilter 110 is configured to receive the modified clock signal S14. Insome embodiments, the modified clock signal S14 is used to coordinateoperations of the loop filter 110. In some embodiments, the modifiedclock signal S14 is used to coordinate operations of the normalizer 112.In some embodiments, the modified clock signal S14 is used to coordinateoperations of the phase error circuit 104. In some embodiments, themodified clock signal S14 is used to coordinate operations of thebandwidth controller 108.

In some embodiments, the PLL is configured to inhibit a loop bandwidthof the PLL from changing from a specified bandwidth. In someembodiments, the loop bandwidth is a closed-loop bandwidth of the PLL.In some embodiments, a stability of the PLL corresponds to a stabilityof the loop bandwidth. In some embodiments, the stability of the PLL isincreased when the stability of the loop bandwidth is increased.

In some embodiments, the loop filter 110 is configured to receive thephase error signal S3 and the modified clock signal S14. In someembodiments, the loop filter 110 is configured to generate a loop filteroutput signal. In some embodiments, the loop filter output signal is anoscillator tuning word (OTW) signal S7 digitally representing an OTW. Insome embodiments, the OTW signal S7 is used by the DCO 114 to generatethe output clock signal S10. In some embodiments, the loop bandwidth isa function of the OTW. In some embodiments, the OTW is a function of aparameter of the loop filter 110. In some embodiments, the OTW is afunction of a loop gain. In some embodiments, the loop bandwidth is afunction of the loop gain. In some embodiments, the loop gain is a gainof the loop filter 110. In some embodiments, the loop gain isprogrammable. In some embodiments, the loop gain is adjustable. In someembodiments, the OTW increases when the loop gain increases. In someembodiments, the loop bandwidth increases when the OTW increases. Insome embodiments, the loop bandwidth increases when the loop gainincreases. In some embodiments, the OTW decreases when the loop gaindecreases. In some embodiments, the loop bandwidth decreases when theOTW decreases. In some embodiments, the loop bandwidth decreases whenthe loop gain decreases.

In some embodiments, the normalizer 112 is configured to receive the OTWsignal S7. In some embodiments, the normalizer 112 is configured tomodify the OTW signal S7 to a normalized OTW signal. In someembodiments, based on the modifying the OTW signal S7, an effect of again of the DCO 114 on the loop bandwidth is mitigated. In someembodiments, the normalizer 112 is configured to undergo aprocess-voltage-temperature (PVT) variation mode of operation to modifythe OTW signal S7 into a first OTW signal S8. In some embodiments, thefirst OTW signal S8 represents a first normalized OTW. In someembodiments, the normalizer 112 is configured to undergo a tracking modeof operation to modify the OTW signal S7 into a second OTW signal S9. Insome embodiments, the second OTW signal S9 represents a secondnormalized OTW.

In some embodiments, when the target frequency changes, the normalizer112 undergoes the PVT variation mode of operation for a first period oftime. In some embodiments, the normalizer 112 does not undergo thetracking mode of operation during the first period of time. In someembodiments, after the first period of time, the normalizer 112undergoes the tracking mode of operation for a second period of time. Insome embodiments, the normalizer 112 does not undergo the PVT variationmode of operation during the second period of time. In some embodiments,the second period of time begins when the PLL is phase-locked. In someembodiments, the second period of time begins before the PLL isphase-locked. In some embodiments, the DCO 114 uses the first OTW signalS8 during the first period of time. In some embodiments, the DCO 114does not use the second OTW signal S9 during the first period of time.In some embodiments, the DCO 114 uses the second OTW signal S9 duringthe second period of time. In some embodiments, the DCO 114 does not usethe first OTW signal S8 during the second period of time.

In some embodiments, the bandwidth controller 108 is configured toreceive the mode control signal S4. In some embodiments, the bandwidthcontroller 108 is configured to calculate a bandwidth control value thatis indicative of a loop filter gain that results in the closed-loopbandwidth of the PLL changing to the specified bandwidth. In someembodiments, the bandwidth controller 108 is configured to generate afirst bandwidth control signal S5 representing the bandwidth controlvalue. In some embodiments, the bandwidth controller 108 is configuredto calculate an estimated DCO gain value that is an estimation of thegain of the DCO 114. In some embodiments, the bandwidth controller 108is configured to generate a second bandwidth control signal S6. In someembodiments, the second bandwidth control signal S6 represents theestimated DCO gain value. In some embodiments, the second bandwidthcontrol signal S6 is used by the normalizer 112 to modify the OTW signalS7 to the normalized OTW signal.

In some embodiments, a change in the modified frequency causes a changein the loop bandwidth. In some embodiments, the loop bandwidth is afunction of the modified frequency. In some embodiments, the loopbandwidth increases when the modified frequency increases. In someembodiments, the loop bandwidth decreases when the modified frequencydecreases.

In some embodiments, the mode value is an integer. In some embodiments,the mode value is a first mode value. In some embodiments, the firstmode value is 0. In some embodiments, when the mode value is the firstmode value, the modified frequency is a first frequency. In someembodiments, the first frequency corresponds to the initial frequency.In some embodiments, the first frequency is substantially equal to theinitial frequency. In some embodiments, the mode value changes to asecond mode value. In some embodiments, the second mode value is 1. Insome embodiments, when the mode value is the second mode value, themodified frequency is a second frequency. In some embodiments, thesecond frequency corresponds to the initial frequency divided by 2. Insome embodiments, the second frequency is substantially equal to theinitial frequency divided by 2. In some embodiments, the mode valuechanges to a third mode value. In some embodiments, the third mode valueis 2. In some embodiments, when the mode value is the third mode value,the modified frequency is a third frequency. In some embodiments, thethird frequency corresponds to the initial frequency divided by 4. Insome embodiments, when the third frequency is substantially equal to theinitial frequency divided by 4. In some embodiments, the mode valuechanges to a fourth mode value. In some embodiments, the fourth modevalue is 3. In some embodiments, when the mode value is the fourth modevalue, the modified frequency is a fourth frequency. In someembodiments, the fourth frequency corresponds to the initial frequencydivided by 8. In some embodiments, the fourth frequency is substantiallyequal to the initial frequency divided by 8. In some embodiments, themode value changes to a fifth mode value. In some embodiments, the fifthmode value is 4. In some embodiments, when the mode value is the fifthmode value, the modified frequency is a fifth frequency. In someembodiments, the fifth frequency corresponds to the initial frequencydivided by 16. In some embodiments, the fifth frequency is substantiallyequal to the initial frequency divided by 16. In some embodiments, thefifth mode value is a maximum mode value. In some embodiments, themaximum mode value is greater than the fifth mode value. In someembodiments, the maximum mode value is less than the fifth mode value.In some embodiments, the mode value does not exceed the maximum modevalue.

In some embodiments, the loop bandwidth is substantially equal to thespecified bandwidth when the mode value is a first mode value. In someembodiments, if the mode value is changed to a second mode value, theloop bandwidth changes from the specified bandwidth to a first loopbandwidth. In some embodiments, the second mode value is equal to a sumof 1 and the first mode value. In some embodiments, the first loopbandwidth is substantially equal to half of the specified bandwidth. Insome embodiments, responsive to the mode value being changed, the loopgain is adjusted from a first loop gain to a second loop gain. In someembodiments, the second loop gain is equal to 2 multiplied by the firstloop gain. In some embodiments, after the loop gain is adjusted to thesecond loop gain, the loop bandwidth is substantially equal to thespecified bandwidth. In some embodiments, the mode value being increasedcauses the loop bandwidth to decrease from the specified bandwidth to asecond loop bandwidth. In some embodiments, the second loop bandwidth isless than the specified bandwidth. In some embodiments, responsive tothe mode value being incremented, the loop gain is increased from thesecond loop gain to a third loop gain. In some embodiments, after theloop gain is increased to the third loop gain, the loop bandwidth issubstantially equal to the specified bandwidth.

In some embodiments, if the mode value is incremented, the modifiedfrequency decreases by a factor of a specified number to a firstfrequency. In some embodiments, when the modified frequency decreases tothe first frequency, the loop bandwidth at the specified bandwidthdecreases by a factor of the specified number to a third loop bandwidth.In some embodiments, responsive to the modified frequency decreasing tothe first frequency, the loop gain is increased by a factor of thespecified number to a fourth loop gain. In some embodiments, thespecified number is substantially equal to 2. In some embodiments, afterthe mode value is incremented and the loop gain is increased to thefourth loop gain, the loop bandwidth is substantially equal to thespecified bandwidth. In some embodiments, if the mode value is decreasedto a third mode value, the loop bandwidth increases to a fourth loopbandwidth. In some embodiments, after the mode value is decreased, theloop gain is decreased to a fifth loop gain. In some embodiments, afterthe loop gain is decreased to the fifth loop gain, the loop bandwidth issubstantially equal to the specified bandwidth.

In some embodiments, the loop gain is not adjustable. In someembodiments, when the loop gain is not adjustable, the OTW signal S7 isbased on the modified frequency. In some embodiments, when the loop gainis not adjustable, the loop bandwidth is based on a normalized OTWsignal used by the DCO 114. In some embodiments, the normalizer 112 isconfigured to modify the OTW signal S7 to the normalized OTW signal. Insome embodiments, the effect of the gain of the DCO 114 on the loopbandwidth is mitigated based on the modification of the OTW signal S7 tothe normalized OTW signal. In some embodiments, the loop bandwidth issubstantially equal to the specified bandwidth based on the modificationof the OTW signal S7 to the normalized OTW signal.

In some embodiments, the normalizer 112 is configured to modify the OTWsignal S7 to the normalized OTW signal based on a change of the modevalue. In some embodiments, the loop bandwidth is substantially equal tothe specified bandwidth when the mode value is constant for a period oftime. In some embodiments, if the mode value is changed from a firstmode value to a second mode value, the OTW of the OTW signal S7 ischanged. In some embodiments, based on the modifying the OTW signal S7to the normalized OTW signal, the loop bandwidth is substantially equalto the specified bandwidth. In some embodiments, the first mode value isless than the second mode value. In some embodiments, the second modevalue is equal to a sum of 1 and the first mode value. In someembodiments, when the mode value is changed from the first mode value tothe second mode value, the OTW changes from a first OTW to a second OTW.In some embodiments, the second OTW is less than the first OTW. In someembodiments, the second OTW is half of the first OTW.

In some embodiments, the OTW changing to the second OTW corresponds tothe loop bandwidth changing from the specified bandwidth to a first loopbandwidth. In some embodiments, the first loop bandwidth is less thanthe specified bandwidth. In some embodiments, the first loop bandwidthis half of the specified bandwidth. In some embodiments, the normalizer112 modifies the OTW signal S7 to the normalized OTW signalcorresponding to the loop bandwidth substantially equal to the specifiedbandwidth. In some embodiments, a normalized OTW of the normalized OTWsignal corresponds to the OTW multiplied by a number. In someembodiments, a normalized OTW of the normalized OTW signal issubstantially equal to the OTW multiplied by the number. In someembodiments, the number is an integer. In some embodiments, the numberis a multiple of two. In some embodiments, the number not an integer. Insome embodiments, the number is less than one. In some embodiments, thenumber is greater than zero.

A portion of the normalizer 112 is illustrated in FIG. 3, according tosome embodiments where the loop gain is not adjustable and thenormalizer 112 is configured to modify the OTW signal S7 to thenormalized OTW signal such that the loop bandwidth is substantiallyequal to the specified bandwidth. In some embodiments, the normalizer112 comprises a first multiplexer 302, a second multiplexer 308, a firstmultiplier 304, a second multiplier 312, an adder 306 and a flip-flop310. In some embodiments, the flip-flop 310 is a D flip-flop. In someembodiments, the first multiplexer 302 is configured to receive a firstnormalizer signal S18, a second normalizer signal S19 and a firstmultiplexer control signal S20. In some embodiments, the firstnormalizer signal S18 is generated by a portion of the PLL. In someembodiments, the second normalizer signal S19 is generated by a portionof the PLL. In some embodiments, the first multiplexer control signalS20 is generated by a portion of the PLL. In some embodiments, thesecond multiplexer 308 is configured to receive the OTW signal S7, aflip-flop output signal S24 and a second multiplexer control signal S21.In some embodiments, the second multiplexer control signal S21 isgenerated by a portion of the PLL. In some embodiments, the secondmultiplier 312 is configured to receive a third normalizer signal S25generated by a portion of the PLL.

In some embodiments, the first normalizer signal S18 represents theestimated DCO gain value of the second bandwidth control signal S6described in association with FIG. 1. In some embodiments, the secondnormalizer signal S19 represents the estimated DCO gain value multipliedby a division ratio. In some embodiments, a change of a mode value froma first mode value to a second mode value corresponds to a change of themodified frequency from a first frequency to a second frequency. In someembodiments, the division ratio corresponds to the second frequencydivided by the first frequency. In some embodiments, the division ratiois substantially equal to second frequency divided by the firstfrequency.

In some embodiments, responsive to the change of the mode value, thefirst multiplexer control signal S20 changes. In some embodiments, thefirst multiplexer 302 is configured to generate a first multiplexeroutput signal S26 based on the first normalizer signal S18, the secondnormalizer signal S19 and the first multiplexer control signal S20. Insome embodiments, the first multiplier 304 is configured to generate afirst multiplier output signal S22 based on at least one of the firstmultiplexer output signal S26 or the OTW signal S7. In some embodiments,the first multiplier 304 is configured to multiply the first multiplexeroutput signal S26 with the OTW signal S7 to generate the firstmultiplier output signal S22.

In some embodiments, the third normalizer signal S25 is based on atleast one of the estimated DCO gain value or the division ratio. In someembodiments, the third normalizer signal S25 represents the estimatedDCO gain value multiplied by a difference between the division ratio and1. In some embodiments, responsive to the change of the mode value, thesecond multiplexer control signal S21 changes. In some embodiments, thesecond multiplexer 308 is configured to generate a second multiplexeroutput signal S23 based on at least one of the OTW signal S7, theflip-flop output signal S24 or the second multiplexer control signalS21. In some embodiments, the flip-flop 310 is configured to generatethe flip-flop output signal S24 based on the second multiplexer outputsignal S23 during a previous clock cycle. In some embodiments, thesecond multiplier 312 is configured to generate a second multiplieroutput signal S27 based on at least one of the flip-flop output signalS24 or the third normalizer signal S25. In some embodiments, the secondmultiplier 312 is configured to multiply the flip-flop output signal S24with the third normalizer signal S25 to generate the second multiplieroutput signal S27.

In some embodiments, the adder 306 is configured to generate the secondOTW signal S9 based on at least one of the first multiplier outputsignal S22 or the second multiplier output signal S27. In someembodiments, the adder 306 is configured to add the first multiplieroutput signal S22 and the second multiplier output signal S27 togenerate the second OTW signal S9. In some embodiments, if there is achange in the OTW signal S7 from a first OTW to a second OTW due to thechange of the mode value, the second OTW signal S9 does not change andis equal to the first OTW.

A method 400 of operating a PLL is illustrated in FIG. 4, according tosome embodiments. In some embodiments, at 402, responsive to an FCWsignal being set to an FCW corresponding to a target frequency, avoltage is supplied to one or more portions of the PLL, such that thePLL is turned on. In some embodiments, at 404, the PLL operates using atype-I PLL configuration that is a first-order control systemconfiguration. In some embodiments, at 406, a change in a phase error iscompared with a phase error threshold, the phase error corresponding toa difference between a reference phase and an output phase of an outputclock signal of the PLL. In some embodiments, the PLL operates using thetype-I PLL configuration until a magnitude of the change of the phaseerror is below the phase error threshold.

In some embodiments, at 406, a lock signal is set to a second valueindicating that the PLL is phase-locked when the magnitude of the changeof the phase error is below the phase error threshold. In someembodiments, if the change in the phase error is not less than the phaseerror threshold, then 404 is repeated. In some embodiments, if thechange in the phase error is less than the phase error threshold, thenat 408, the PLL operates using a type-II PLL configuration that is asecond-order control system configuration. In some embodiments, at 410,the change in the phase error is compared with the phase error thresholdand the lock signal is set to the second value when the magnitude of thechange in the phase error is below the phase error threshold. In someembodiments, if the change in the phase error is not less than the phaseerror threshold, then 408 is repeated.

In some embodiments, if the change in the phase error is less than thephase error threshold, then at 412, a mode value is increased from afirst mode value to a second mode value and a clock adjuster modifies aninitial clock signal with an initial frequency to a modified clocksignal having a modified frequency substantially equal to a firstfrequency. In some embodiments, the modified frequency corresponds tothe initial frequency divided by a specified divisor. In someembodiments, the modified frequency is equal to the initial frequencydivided by the specified divisor. In some embodiments, the specifieddivisor corresponds to 2 to the power of the mode value. In someembodiments, the specified divisor is equal to 2 to the power of themode value. In some embodiments, the first mode value is equal to 0. Insome embodiments, the second mode value is equal to 1. In someembodiments, the first frequency corresponds to the initial frequencydivided by 2 to the power of the second mode value. In some embodiments,the first frequency is equal to the initial frequency divided by two.

In some embodiments, responsive to the mode value changing, a normalizedOTW is adjusted by a normalizer. In some embodiments, based on adjustingthe normalized OTW by the normalizer, a loop bandwidth is substantiallyequal to a specified bandwidth. In some embodiments, at 414, responsiveto the mode value changing, a loop gain is adjusted to a first loopgain. In some embodiments, based on adjusting the loop gain, the loopbandwidth is substantially equal to the specified bandwidth. In someembodiments, at 416, the PLL operates with the modified frequencysubstantially equal to the first frequency and the loop bandwidthsubstantially equal to the specified bandwidth. In some embodiments, at418, the change in the phase error is compared with the phase errorthreshold and the lock signal is set to the second value when themagnitude of the change in the phase error is below the phase errorthreshold. In some embodiments, if the change in the phase error is notless than the phase error threshold, then 416 is repeated. In someembodiments, if the change in the phase error is less than the phaseerror threshold, then at 420, the PLL is phase-locked. In someembodiments, after the lock signal is set to the second value, if themode value is a maximum mode value, the PLL is configured to continueoperation with the modified frequency substantially equal to the firstfrequency.

In some embodiments, if the mode value is below the maximum mode value,the mode value is increased to a third mode value, and the clockadjuster modifies the initial clock signal to a second clock signalhaving a second frequency. In some embodiments, the second frequencycorresponds to the initial frequency divided by a second specifieddivisor. In some embodiments, the second specified divisor is the sameas the specified divisor. In some embodiments, the second specifieddivisor is different than the specified divisor. In some embodiments,the second frequency is equal to the initial frequency divided by thesecond specified divisor. In some embodiments, the second specifieddivisor corresponds to 2 to the power of the third mode value. In someembodiments, the second specified divisor is equal to 2 to the power ofthe third mode value. In some embodiments, responsive to the mode valuechanging, the normalized OTW is adjusted by the normalizer. In someembodiments, based on adjusting the normalized OTW by the normalizer,the loop bandwidth is substantially equal to the specified bandwidth. Insome embodiments, responsive to the mode value changing, the loop gainis adjusted to a second loop gain. In some embodiments, based onadjusting the loop gain, the loop bandwidth is substantially equal tothe specified bandwidth.

A method 500 of operating a PLL is illustrated in FIG. 5, according tosome embodiments. In some embodiments, the PLL is phase-locked and amode value is below a maximum mode value. In some embodiments, if themode value is the maximum mode value, a modified frequency of a modifiedclock signal is substantially equal to a minimum modified frequency ofthe modified clock signal. In some embodiments, the minimum modifiedfrequency corresponds to an initial frequency of an initial clock signaldivided by 2 to the power of the maximum mode value. In someembodiments, the minimum modified frequency is equal to the initialfrequency of the initial clock signal divided by 2 to the power of themaximum mode value.

In some embodiments, a power usage of the PLL is a function of themodified frequency. In some embodiments, as the modified frequencydecreases the power usage decreases. In this way, in some embodiments,at 502, the mode value is changed to the maximum mode value to decreasethe power usage. In some embodiments, responsive to the mode valuechanging at 502, a normalized OTW is adjusted by a normalizer. In someembodiments, based on adjusting the normalized OTW by the normalizer, aloop bandwidth is substantially equal to a specified bandwidth. In someembodiments, responsive to the mode value changing at 502, a loop gainis adjusted to a first loop gain at 504. In some embodiments, based onadjusting the loop gain, the loop bandwidth is substantially equal tothe specified bandwidth.

In some embodiments, at 506, a change of an FCW occurs corresponding toa change of a target frequency. In some embodiments, if the mode valueis a minimum mode value, the modified frequency is equal to a maximummodified frequency of the modified clock signal. In some embodiments,the maximum modified frequency corresponds to the initial frequencydivided by 2 to the power of the minimum mode value. In someembodiments, the maximum modified frequency is equal to the initialfrequency divided by 2 to the power of the minimum mode value. In someembodiments, the maximum modified frequency is substantially equal tothe initial frequency. In some embodiments, an acquisition time is afunction of the modified frequency. In some embodiments, the acquisitiontime is equal to an amount of time between the change of a targetfrequency and the PLL being phase-locked. In some embodiments, as themodified frequency decreases the acquisition time increases. In someembodiments, as the modified frequency increases, the acquisition timedecreases.

In some embodiments, at 508, responsive to the change of the targetfrequency, the mode value is changed to the minimum mode value todecrease the acquisition time. In some embodiments, responsive to themode value changing at 508, the normalized OTW is adjusted by thenormalizer. In some embodiments, based on adjusting the normalized OTWby the normalizer, the loop bandwidth is substantially equal to thespecified bandwidth. In some embodiments, responsive to the mode valuechanging at 508, the loop gain is adjusted to a second loop gain at 510.In some embodiments, based on adjusting the loop gain at 510, the loopbandwidth is substantially equal to the specified bandwidth.

A method 600 of operating a PLL is illustrated in FIG. 6, according tosome embodiments. In some embodiments, at 602, a change in a phase errorsignal of the PLL is compared to an error threshold. In someembodiments, responsive to determining that the change is below theerror threshold, at 604, an initial clock signal of the PLL having aninitial frequency is modified to a first clock signal having a firstfrequency to alter power usage of the PLL. In some embodiments, theinitial clock signal being modified to the first clock signal causes abandwidth of the PLL to change from a specified bandwidth to a bandwidthdifferent than the specified bandwidth. In some embodiments, responsiveto the modifying an initial clock signal, at 606, the bandwidth ismodified to the specified bandwidth.

A method 700 of operating a PLL is illustrated in FIG. 7, according tosome embodiments. In some embodiments, at 702, a first clock signalhaving a first frequency is outputted. In some embodiments, the firstclock signal is outputted by a clock adjuster. In some embodiments,responsive to determining a change of a target frequency represented bya signal, at 704, a second clock signal having a second frequency isoutputted to alter an acquisition time required for the PLL to becomephase-locked.

In some embodiments, a PLL is provided comprising a clock adjuster and aloop filter. In some embodiments, the clock adjuster is configured toreceive an initial clock signal having an initial frequency. In someembodiments, the clock adjuster is configured to receive a mode controlsignal. In some embodiments, the clock adjuster is configured to modifythe initial clock signal to a first clock signal based on the modecontrol signal, responsive to a change in a phase error signal of thePLL being below an error threshold, the first clock signal having afirst frequency. In some embodiments, the loop filter is configured togenerate a loop filter output signal based on the first clock signal,the loop filter output signal controlling a bandwidth of the PLL.

In some embodiments, a method for operating a PLL is provided. In someembodiments, the method comprises comparing a change in a phase errorsignal of the PLL to an error threshold. In some embodiments, the methodcomprises responsive to determining that the change is below the errorthreshold, modifying an initial clock signal of the PLL having aninitial frequency to a first clock signal having a first frequency toalter power usage of the PLL. In some embodiments, the method comprisesresponsive to the modifying an initial clock signal, modifying abandwidth of the PLL to a specified bandwidth.

In some embodiments, a method for operating a PLL is provided. In someembodiments, the method comprises outputting a first clock signal of thePLL having a first frequency. In some embodiments, the method comprisesresponsive to determining a change of a target frequency represented bya signal, outputting a second clock signal having a second frequency toalter an acquisition time required for the PLL to become phase-locked.

The foregoing outlines features of several embodiments so that those ofordinary skill in the art may better understand various aspects of thepresent disclosure. Those of ordinary skill in the art should appreciatethat they may readily use the present disclosure as a basis fordesigning or modifying other processes and structures for carrying outthe same purposes and/or achieving the same advantages of variousembodiments introduced herein. Those of ordinary skill in the art shouldalso realize that such equivalent constructions do not depart from thespirit and scope of the present disclosure, and that they may makevarious changes, substitutions, and alterations herein without departingfrom the spirit and scope of the present disclosure.

Although the subject matter has been described in language specific tostructural features or methodological acts, it is to be understood thatthe subject matter of the appended claims is not necessarily limited tothe specific features or acts described above. Rather, the specificfeatures and acts described above are disclosed as example forms ofimplementing at least some of the claims

Various operations of embodiments are provided herein. The order inwhich some or all of the operations are described should not beconstrued to imply that these operations are necessarily orderdependent. Alternative ordering will be appreciated having the benefitof this description. Further, it will be understood that not alloperations are necessarily present in each embodiment provided herein.Also, it will be understood that not all operations are necessary insome embodiments.

Moreover, “exemplary” is used herein to mean serving as an example,instance, illustration, etc., and not necessarily as advantageous. Asused in this application, “or” is intended to mean an inclusive “or”rather than an exclusive “or”. In addition, “a” and “an” as used in thisapplication and the appended claims are generally be construed to mean“one or more” unless specified otherwise or clear from context to bedirected to a singular form. Also, at least one of A and B and/or thelike generally means A or B or both A and B. Furthermore, to the extentthat “includes”, “having”, “has”, “with”, or variants thereof are used,such terms are intended to be inclusive in a manner similar to the term“comprising”. Also, unless specified otherwise, “first,” “second,” orthe like are not intended to imply a temporal aspect, a spatial aspect,an ordering, etc. Rather, such terms are merely used as identifiers,names, etc. for features, elements, items, etc. For example, a firstelement and a second element generally correspond to element A andelement B or two different or two identical elements or the sameelement.

Also, although the disclosure has been shown and described with respectto one or more implementations, equivalent alterations and modificationswill occur to others of ordinary skill in the art based upon a readingand understanding of this specification and the annexed drawings. Thedisclosure comprises all such modifications and alterations and islimited only by the scope of the following claims. In particular regardto the various functions performed by the above described components(e.g., elements, resources, etc.), the terms used to describe suchcomponents are intended to correspond, unless otherwise indicated, toany component which performs the specified function of the describedcomponent (e.g., that is functionally equivalent), even though notstructurally equivalent to the disclosed structure. In addition, while aparticular feature of the disclosure may have been disclosed withrespect to only one of several implementations, such feature may becombined with one or more other features of the other implementations asmay be desired and advantageous for any given or particular application.

What is claimed is:
 1. A phase-locked loop (PLL), comprising: a clockadjuster configured to: receive an initial clock signal having aninitial frequency; receive a mode control signal; and responsive to achange in a phase error signal of the PLL being below an errorthreshold, modify the initial clock signal to a first clock signal basedon the mode control signal, the first clock signal having a firstfrequency; and a loop filter configured to generate a loop filter outputsignal based on the first clock signal, the loop filter output signalcontrolling a bandwidth of the PLL.
 2. The PLL of claim 1, the loopfilter configured to use the first clock signal to coordinate one ormore operations.
 3. The PLL of claim 1, the first frequencycorresponding to the initial frequency divided by a specified divisor,the specified divisor based on the mode control signal.
 4. The PLL ofclaim 3, the specified divisor corresponding to 2 to the power of avalue of the mode control signal.
 5. The PLL of claim 1, comprising aphase error circuit configured to: receive a reference phase signalrepresenting a reference phase; receive a first output phase signalrepresenting a fractional part of an output phase; receive a secondoutput phase signal representing an integer part of the output phase;and output the phase error signal based on at least one of the referencephase signal, the first output phase signal or the second output phasesignal.
 6. The PLL of claim 5, the phase error circuit comprising asubtractor configured to subtract the fractional part of the outputphase and the integer part of the output phase from the reference phaseto generate the phase error signal.
 7. The PLL of claim 5, comprising amode controller comprising: a lock detection circuit configured to:receive the phase error signal; and provide a lock signal based on thephase error signal and the error threshold; and a finite-state machineconfigured to: receive the lock signal; and generate the mode controlsignal based on the lock signal.
 8. The PLL of claim 7, the lockdetection circuit comprising: a flip-flop configured to generate a firstsignal representing a stored phase error based on the phase error signalduring a previous clock cycle; a subtractor configured to generate asecond signal representing a change in a phase error of the phase errorsignal based on a difference between the stored phase error and thephase error; and a comparator configured to compare the change in thephase error with the error threshold to generate the lock signal.
 9. ThePLL of claim 1, the loop filter output signal representing an oscillatortuning word (OTW).
 10. The PLL of claim 1, the loop filter configured toadjust the bandwidth to correspond to a specified bandwidth.
 11. The PLLof claim 1, the loop filter configured to adjust the bandwidth based ona first bandwidth control signal.
 12. The PLL of claim 11, comprising abandwidth controller configured to generate the first bandwidth controlsignal based on the mode control signal.
 13. The PLL of claim 12, thebandwidth controller configured to: determine a digitally controlledoscillator (DCO) gain estimate corresponding to a gain of a DCO of thePLL; and generate a second bandwidth control signal based on the DCOgain estimate.
 14. The PLL of claim 13, comprising a gain normalizerconfigured to: receive the second bandwidth control signal; receive theloop filter output signal; and generate a normalized oscillator tuningword (OTW) signal, representing a normalized OTW, based on the secondbandwidth control signal and the loop filter output signal.
 15. A methodfor operating a phase-locked loop (PLL), comprising: comparing a changein a phase error signal of the PLL to an error threshold; responsive todetermining that the change is below the error threshold, modifying aninitial clock signal of the PLL having an initial frequency to a firstclock signal having a first frequency to alter power usage of the PLL;and responsive to the modifying an initial clock signal, modifying abandwidth of the PLL to a specified bandwidth.
 16. The method of claim15, comprising modifying an oscillator tuning word (OTW) to reduce animpact of the modifying an initial clock signal on the bandwidth. 17.The method of claim 15, comprising modifying an oscillator tuning word(OTW) of the PLL to mitigate an impact of a digitally controlledoscillator (DCO) of the PLL on the bandwidth.
 18. A method for operatinga phase-locked loop (PLL), comprising: outputting a first clock signalof the PLL having a first frequency; and responsive to determining achange of a target frequency represented by a signal, outputting asecond clock signal having a second frequency to alter an acquisitiontime required for the PLL to become phase-locked.
 19. The method ofclaim 18, the first clock signal different than the second clock signal,the first frequency different than the second frequency.
 20. The methodof claim 18, the outputting a second clock signal performed after theoutputting a first clock signal.